// Copyright DustedPixels.com 2008. All rights reserved.

package com.dustedpixels.jasmin.unit.z80.v1;

/**
 * @author micapolos@gmail.com (Michal Pociecha-Los)
 */
public final class MicroCode {
  // Input
  public int OPCODE;
  public int MCYCLE;
  
  public int MCYCLES;
  public int TCYCLES;
  
  public int REGS_REG_IN;
  public int REGS_MODE_IN;
  public int REGS_REG_OUT;
  public int REGS_MODE_OUT;
  
  public boolean REGS_ENABLE;
  public boolean REGS_WR;
  
  public boolean AF_ENABLE;
  public boolean AF_WR;
  public int AF_IN;
  public int AF_OUT;
  public static final int AF_ACC = 0;
  public static final int AF_FLAGS = 1;
  
  public int DATA_MUX;
  public static final int DATA_MUX_ZERO  = 0;
  public static final int DATA_MUX_REGS  = 1;
  public static final int DATA_MUX_ACC   = 2;
  public static final int DATA_MUX_FLAGS = 3;
  public static final int DATA_MUX_TMP   = 4;
  
  public boolean LD_R_R; // exchange registers
  public boolean LD_R;   // load register from data bus
  public boolean INC_PC; // increment PC
  public int SSS;        // source register
  public int DDD;        // destination register
  public boolean LD_ADDR_HL;  // load HL/IX/IY onto address bus
  public boolean LD_DATA_R;   // load register onto data bus
  public boolean WRITE;       // memory write
  
  
  public void update() {
    
    /* ----------------------------- *
     * Instruction decoding routines *
     * ----------------------------- */
    switch (OPCODE) {
      case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x47:
      case 0x48: case 0x49: case 0x4A: case 0x4B: case 0x4C: case 0x4D: case 0x4F:
      case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x57:
      case 0x58: case 0x59: case 0x5A: case 0x5B: case 0x5C: case 0x5D: case 0x5F:
      case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x67:
      case 0x68: case 0x69: case 0x6A: case 0x6B: case 0x6C: case 0x6D: case 0x6F:
      case 0x78: case 0x79: case 0x7A: case 0x7B: case 0x7C: case 0x7D: case 0x7F:
        // LD r,r
        if (MCYCLE == 1) {
          LD_R_R = true;
          SSS = OPCODE & 0x07;
          DDD = (OPCODE >> 3) & 0x07;
        }
        break;
      case 0x06: case 0x0E: case 0x16: case 0x1E: case 0x26: case 0x2E: case 0x3E:
        // LD r,n
        switch (MCYCLE) {
          case 1:
            break;
          case 2:
            INC_PC = true;
            LD_R = true;
            DDD = (OPCODE >> 3) & 0x07;            
            break;
        }
        break;
      case 0x46: case 0x4E: case 0x56: case 0x5E: case 0x66: case 0x6E: case 0x7E:
        // LD r,(HL)
        switch (MCYCLE) {
          case 1:
            LD_ADDR_HL = true;
            break;
          case 2:
            LD_R = true;
            DDD = (OPCODE >> 3) & 0x07;            
            break;
        }
        break;
      case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
        // LD (HL),r
        switch (MCYCLE) {
          case 1:
            LD_ADDR_HL = true;
            SSS = OPCODE & 0x07;
            LD_DATA_R = true;
            break;
          case 2:
            WRITE = true;
            break;
        }
        break;
    }
  }
}
